1. Field of the Invention
This invention relates to a circuit for stabilizing current, and more particularly to a power gating apparatus for in-rush current mitigation.
2. Description of the Prior Art
Currently, the system-on-a-chip (SOC) applied in telecommunication products or in computers is developing in the trend of high performance and portability, and thus its power consumption has become an important consideration in design. The most effective way to reduce the power consumption of a circuit is to reduce the operating voltage of the circuit. However, if the operating voltage is lowered, the overall performance of the circuit will be lowered accordingly. Therefore, in order to maintain the overall performance of the circuit, threshold voltages of transistors must be lowered, which will lead to an indexed growth of the sub-threshold leakage current.
Due to the nanoscale nature of semiconductor development processing, power consumption sharply increases due to leakage current. In order to reduce the leakage current, a technique referred to as power gating is used to cut off power supplied to a circuit block that is not currently used in a chip.
It is known to provide integrated circuits with one or more virtual power rails and one or more virtual ground rails. These virtual rails are selectively connected or disconnected to the main power rails and the main ground rails respectively by header transistors and footer transistors. This technique is useful in reducing power consumption when a block/domain within an integrated circuit is not required to be active and accordingly can be powered down and isolated from the power supply and the ground by the use of these header and/or footer transistors. These header and/or footer devices are selected such that when they are switched off they have a high resistance and thus, a low leakage current. This is generally done by selecting devices with a high threshold voltage.
Accordingly, those skilled in the art seek methods and apparatus that are capable of controlling integrated circuits incorporating power gating technology in such a manner that reacts to the dynamic conditions being experienced by the power gating circuitry.
FIG. 1 shows a circuit for in-rush current mitigation according to the prior art. Small switch cells 11 receive power and “Sleep” signal, and after a Schmitt trigger 13 detects voltage signal, a logic unit 14 enable/disable big switch cells 12. The extra Schmitt trigger compromises the IC design in some applications.
FIG. 2 shows a circuit for in-rush current mitigation according to another prior art. The methodology to mitigate in-rush current is to utilize so-called “Mother/Daughter” switch cell, which has two switches of different size inside (one small switch is named “Daughter” and another bigger one is named “Mother”). When all switch cells are turn-on, the Daughter's input 211 in switch cell 21 receives SleepEn signal and the Daughter's output 212 transmits it to the next switch cell 22 having a corresponding Daughter's input 221 and Daughter's output 222 which is then transmitted to switch cell 23 having a corresponding Daughter's input 231 and Daughter's output 232 and so on. As going on the last switch cell's 29 Daughter's input 291 receives SleepEn signal and the Daughter's output 292 transmits it back to the Mother's input 293 in same switch cell 29. From the Mother's output 294 the SleepEn signal is transferred to the Mother's input 213 in switch cell 21 via switch cells 28-22 and corresponding Mother's inputs 283, 273, 264, 254, 244, 233, and 223 and Mother's outputs 284, 274, 263, 253, 243, 234, and 224 and goes out an ACK signal from the Mother's output 214. FIG. 3A indicates the I-V curve at Daughter's input 291 when switching on Daughter switches only. FIG. 3B indicates the I-V curve at the Mother's input 293 as switching on Mother switches only.
In order to fit nowadays' specification, switch cells should be used in design. However, there is large in-rush current while maintaining ramp-up time. “In-rush current” could compromise the power network integrity. It needs to reduce in-rush current to acceptable one, such that this design could meet specifications.